In a TFT-LCD source driver circuit in general, a liquid crystal panel is driven as follows. Namely, a display-use signal is digitally processed by a logic circuit which is operated by a power source voltage of approximately 3V. Then, the signal is converted into a voltage of approximately 10V which is required for driving a liquid crystal panel of the TFT-LCD.
FIG. 8 illustrates an exemplary configuration of a TFT-LCD module. In the TFT-LCD module, a control circuit 102 controls a plurality of gate driver circuits 103 . . . and a plurality of source driver circuits 104 . . . , so that the gate driver circuits 103 . . . and the source driver circuits 104 . . . drive a liquid crystal panel 101.
FIG. 9 illustrates a configuration of each of the source driver circuits 104. Each source driver circuit 104 includes, sequentially from a side of the control circuit 102 towards a side of the liquid crystal panel 101: shift registers 104a . . . ; sampling latch circuits 104b . . . ; hold latch circuits 104c . . . ; level shifting circuits 104d . . . ; DA converter circuits 104e . . . ; and output amplifiers 104f . . . . 
Further, FIG. 10 illustrates an exemplary configuration of the TFT-LCD source driver circuit 104 for each output terminal. In the following explanation with reference to FIG. 10, it is assumed that display data is in 6 bits. For each bit of the 6 bit display data, one of the sampling latch circuits 104b . . . , one of the hold latch circuits 104c . . . , and one of the level shifting circuit 104d are provided.
Each bit of the display data is sampled in the sampling latch circuit 104b based on a start pulse signal transmitted through the shift register 104a (not shown). Then, in the hold latch circuit 104c, each of the 6 bits are latched based on a latch signal (horizontal sync. signal) (not shown). After a signal level of the display data is converted in the level shifting circuit 104d, a voltage for tone display is selected in accordance with the display data (6 bits in this case), in the DA converter circuit 104e. Then, a low-impedance process is carried out in the output amplifier 104f (voltage follower circuit in FIG. 10), and the display data is outputted to the liquid crystal panel 101.
In FIG. 10, the shift register 104a, the sampling latch circuit 104b, and the hold latch circuit 104c are conventionally a logic circuit which is operated by the power source voltage of approximately 3V. Further, the DA converter circuit 104e and the output amplifier 104f are analogue circuit which is operated by the power source voltage of approximately 10V. Accordingly, it is necessary to provide, between the logic circuit and the analogue circuit, the level shifting circuit 104d which converts a logic signal of 3V into a logic signal of 10V.
Next, the following describes, with reference to FIG. 4, a first conventional example of a level shifting circuit (See, for example, Japanese Unexamined Patent Application No. 4-284021/1992 (Tokukaihei 4-284021; published on Oct. 8, 1992)). A level shifting circuit 111 of FIG. 4 includes: P-channel MOS transistors MP 111, MP 112, MP113, and MP 114; N-channel MOS transistors MN 111 and MN 112; and an inverter 112. The source of the MOS transistor MP 111 is connected to a 10V-power supply, and the drain of the MOS transistor MP 111 is connected to the source of the MOS transistor MP113. The gate of the MOS transistor MP 111 is connected to a connection point-b of the MOS transistor MP 114 and the MOS transistor MN 112.
The drain of the MOS transistor MP113 is connected to the drain of the MOS transistor MN 111, and the source of the MOS transistor MN 111 is connected to a GND. The gates of the MOS transistors MP113 and MN 111 are connected to an input terminal IN of the level shifting circuit 111.
The source of the MOS transistor MP 112 is connected to the 10V-power supply, and the drain of the MOS transistor MP 112 is connected to the source of the MOS transistor MP 114. The gate of the MOS transistor MP 112 is connected to a connection point-a of the MOS transistor 113 and the MOS transistor MN 111.
The drain of the MOS transistor MP114 is connected to the drain of the MOS transistor MN 112, and the source of the MOS transistor MN 112 is connected to the GND. The gates of the MOS transistors MP114 and MN 112 are connected, via the inverter 112, to an input terminal IN of the level shifting circuit 111.
Further, the gate of the MOS transistor MP 112, and the connection point of the MOS transistor MP 113 and MN 111 serve as an output terminal OUT of the level shifting circuit 111.
In the level shifting circuit 111, for example, when a voltage of a small amplitude (e.g., 3V to 5V) is inputted to the input terminal IN, a voltage of 10V in amplitude is outputted from the output terminal OUT. When a low-level voltage is inputted to the input terminal IN, the MOS transistors MP 111, MP113, MN 112 are switched to the ON state, while the MOS transistors MP 112, MP 114, and MN 111 are switched to the OFF state, thus outputting the voltage of 10V from the output terminal OUT.
Here, FIG. 5 illustrates an example where the circuit configuration of FIG. 4 is applied to a TFT-LCD source driver circuit. A TFT-LCD source driver circuit 121 includes: a sampling latch circuit 122; a hold latch circuit 123; a level shifting circuit 111; and an output buffer circuit 125.
The sampling latch circuit 122 includes: a tri-state inverters 122a and 122b; and an inverter 122c. In the tri-state inverter 122a, a sampling signal SMP is used as a clock signal, and an inverted signal of the sampling signal SMP is used as an inverted clock signal. Further, in the tri-state inverter 122b, the sampling signal SMP is used as the inverted clock signal, and the inverted signal of the sampling signal SMP is used as a clock signal. An output from the tri-state buffer 122a is inputted to the inverter 122c, and an output from the inverter 122c is inputted to the hold latch circuit 123. Further, the output from the inverter 122c is also inputted to the tri-state inverter 122b, and an output from the tri-state inverter 122b is inputted to the inverter 122c. 
The hold latch circuit 123 includes: tri-state inverters 123a and 123b; and an inverter 123c. In the tri-state inverter 123a, a strobe signal SRT is used as a clock signal, and an inverted signal of the strobe signal SRT is used as an inverted clock signal. Further, in the tri-state inverter 123b, the strobe signal SRT is used as an inverted clock signal, and the inverted signal of the strobe signal SRT is used as the clock signal. An output from the tri-state buffer 123a is inputted to the inverter 123c, and an output from the inverter 123c is inputted to the level shifting circuit 111, via the inverter 124. Further, the output from the inverter 123c is also inputted to the tri-state inverter 123b, and an output from the tri-state inverter 123b is inputted to the inverter 123c. 
The level shifting circuit 111 performs the operation which has already been mentioned above, and the output therefrom is inputted to the output buffer circuit 125. The output buffer circuit 125 is a stage in which an inverter 126 and an inverter 127 are cascade-connected with each other. The inverter 126 is a CMOS inverter including a P-channel MOS transistor MP 126 and an N-channel MOS transistor MN 126. An output from the level shifting circuit is inputted to the gates of the MOS transistors MP 126 and MN 126. The output from the inverter 126 is outputted as an output signal/OUT (“/” represents a bar), and is inputted to the inverter 127. The inverter 127 is a CMOS inverter including a P-channel MOS transistor MP 127 and an N-channel MOS transistor MN 127. The output from the inverter 126 is inputted to the gates of the MOS transistors MP 127 and MN127. The output from the inverter 127 is outputted, as an output signal OUT, to a next circuit.
In the TFT-LCD source driver circuit 121, the sampling latch circuit 122, the hold latch circuit 123, and the inverters 124, and 112 constitute a 3V-logic circuit. Further, members of the level shifting circuit 111 other than the inverter 112, and the output buffer circuit 125 constitute a 10V-medium-voltage resilient circuit.
Next, the following deals with a second conventional example using a precharge-type level shifting circuit which uses a dynamic sampling circuit. FIG. 6 illustrates a dynamic decoding circuit 131 which is commonly used in an address decoder of a memory. This circuit is applicable to a level shifting circuit. The dynamic decoding circuit 131 includes: a P-channel MOS transistor MP 131; an N-channel MOS transistor MN 131; N-channel MOS transistors MN 132(0) to MN 132(n−1); and a load capacitor C131.
The source of the MOS transistor MP 131 is connected to a power supply of a higher electric potential, and the drain of the MOS transistor MP 131 is connected to the drain of the MOS transistor MN 131. The source of the MOS transistor MN 131 is connected to the drain of the MOS transistor MN 132(n−1). The MOS transistors MN 132(0) to MN132(n−1) are sequentially and serially connected from the GND to the source of the MOS transistor MN 131. A precharge signal/PRE is inputted to the gates of the MOS transistors MP 131 and MN131. Further, data sets D(0) to D(n−1) are respectively inputted to the gates of the MOS transistors MN 132(0) to MN132(n−1). The load capacitor C131 is a capacitor connected to the wiring extended from a connection point, of the MOS transistor MP 131 and the MOS transistor MN 131, to an output terminal OUT. It is assumed that a capacitance of this load capacitor C131 includes a parasitic capacitance of the circuit including: a parasitic capacitance of the wiring; and a parasitic capacitance of an element connected to the wiring.
An exemplary technology for applying the dynamic decoding circuit 131 to a level shifting circuit is disclosed in, for example, Japanese Unexamined Patent Publication No. 115758/2003 (Tokukai 2003-115758; Published on Apr. 18, 2003). FIG. 7 is a circuit diagram of the technology. A level shifting circuit 141 illustrated in FIG. 7 includes: P-channel MOS transistors MP141 and MP142; N-channel MOS transistors MN141 to MN144; and load capacitors C141 and C142.
The source of the MOS transistor MP 141 is connected to a 10V-power supply, and the drain of the MOS transistor MP 141 is connected to the drain of the MOS transistor MN 143. The source of the MOS transistor MN143 is connected to the drain of the MOS transistor 142, and the source of the MOS transistor 142 is connected to a GND. The MOS transistor MN 141 is connected between an input terminal IN and the gate of the MOS transistor MN 142. The load capacitor C141 is connected to wiring between the gate of the MOS transistor MN 142 and the MOS transistor MN 141. The load capacitor C141 includes a parasitic capacitance of the wiring.
The source of the MOS transistor MP 142 is connected to the 10V-power supply, and the drain of the MOS transistor MP 142 is connected to the drain of the MOS transistor MN 144. The source of the MOS transistor MN 144 is connected to the GND. The gates of the MOS transistor MP142 and MN144 are connected to a connection point of the MOS transistor MP 141 and the MOS transistor MN 143, and the load capacitor C142 is a capacitor connected to wiring connecting the gates and the connection point. This load capacitor C142 includes a parasitic capacitance of the circuit including: a parasitic capacitance of the wiring; and a parasitic capacitance of an element connected to the wiring.
The connection point of the MOS transistor MP 142 and the MOS transistor MN 144 serves as an output terminal OUT. For example, a voltage of 3V in amplitude is inputted to the input terminal IN. A sampling pulse signal SMP is inputted to the gates of the MOS transistor MP 141 and the MOS transistor MN 143. An inverted signal XSMP of the sampling pulse signal SMP is inputted to the gate of the MOS transistor MN 141.
Next described is a basic operation of the level shifting circuit 141 illustrated in FIG. 7. For example, when the sampling pulse signal SMP is a low level, and the inverted signal XSMP is at a high level (10V) as such, the precharge-use MOS transistor MP 141 is switched to the ON state, and the MOS transistor MN 141 is also switched to the ON state. Meanwhile, the MOS transistor MN 143 is switched to the OFF state. Accordingly, the load capacitor C142 is charged by the 10V power supply, via the MOS transistor MP 141, so that the load capacitor C142 is precharged to the power supply voltage of 10V. Further, since the MOS transistor MN 141 is in the ON state, an electric potential of an input signal IN (0V to 3V) is applied to the load capacitor C141, as a terminal voltage, thus charging the load capacitor C141.
Next, when the sampling pulse signal SMP is the high level (the inverted signal XSMP is the low level), the MOS transistor MN 141 is switched to the OFF state, and the load capacitor C141 is electrically disconnected from the input terminal IN. Further, the evaluation-use MOS transistor MN 143 is switched to the ON state, and the precharge-use MOS transistor MP 141 is switched to the OFF state. Further, the load capacitor C142 is connected to the GND via the MOS transistors MN 143 and MN142.
At this point, the load capacitor C142 retains the precharged terminal voltage of 10V, or discharges the precharged terminal voltage of 10V down to 0V, in accordance with the electric potential (0V or 3V) of the input signal retained in the load capacitor C141. That is, while the terminal voltage of the load capacitor C141 is 3V, the MOS transistor MN 142, whose gate accepts the terminal voltage of the load capacitor C141, is switched to the ON state. Then, the load capacitor C142 discharges the electric potential stored therein, and the terminal voltage of the load capacitor C142 drops down to the GND potential. Accordingly, the MOS transistor MP 142 which accepts the gate electric potential of 0V is switched to the ON state, and the MOS transistor MN 144 is switched to the OFF state. As a result, the output from the output terminal OUT is the high level (10V). In the process in which the load capacitor C142 discharges the electric potential stored therein, the MOS transistor MP 142 is switched to the ON state when the terminal voltage drops from 10V by a threshold voltage of the MOS transistor MP 142, and the signal voltage of the output terminal OUT starts to rise.
On the contrary, when the terminal voltage of the load capacitor C141 is 0V, the MOS transistor MN 142 is switched to the OFF state, and the electric potential stored in the load capacitor C142 is retained at its terminal voltage of 10V. Further, the MOS transistor MP 142 which accepts the gate electric potential of 10V is switched to the OFF state, and the MOS transistor MN 144 is switched to the ON state. As a result, the signal voltage of the output terminal OUT is 0V. As described, a signal of 10V or 0V can be obtained from the output terminal OUT, in accordance with the electric potential of the input signal at the input terminal IN. Further, in the process in which the load capacitor C142 is precharged with the electric charge to be stored, the MOS transistor MN 144 switched to the ON state, and the signal voltage of the output terminal OUT falls, when the terminal voltage surpasses the threshold voltage of the MOS transistor MN 144.
In the level shifting circuit 111 of the first conventional example, the ON/OFF state of the MOS transistors switches when the voltage level inputted to the input terminal IN transits from the low level to the high level. In view of that, the MOS transistor MP113 whose channel serves as a resistor is provided, so as to: restrain an increase in the electric potential of the connection point a of the MOS transistor MP113 and the MOS transistor MN 111; prevent the MOS transistor MP 112 which needs to be in the ON state from being switched to the OFF state; and avoid a delay in switching the ON/OFF state from the OFF state to the ON state. Similarly, the MOS transistor MP 114 is also provided so that its channel serves as a resistor.
In the first conventional example, the level shifting circuit of FIG. 4 is used. However, in order to ensure a normal electrical properties of the circuit, the MOS transistors MP113 and the MP 114 which serve as the resistor need to be an MOS transistor having a long gate length. Further, in order to achieve a sufficiently low ON-resistance, the MOS transistor MN 111 and the MN 112, whose amplitude of the gate signal is small (voltage level of 3V to 5V), need to be an MOS transistor having a wide gate width. However, all of these MOS transistors are transistors having a large element size, in order to tolerate a high operation voltage. Increasing of the gate length and the gate width of these transistors will cause a significant increase in the planar dimension of the circuit, which consequently enlarges the size of a chip, in a case of forming the circuit into an LSI circuit.
Further, a dynamic sampling circuit is used in the second conventional example of FIG. 7, so as to form so-called a dynamic sampling type level shifting circuit. In this circuit, the sampling pulse signal SMP, during the precharging period, needs to drop down to GND electric potential which switches the MOS transistor MN 143 to the OFF state. On the other hand, the sampling pulse signal SMP, during the data sampling period, needs to rise up to the power supply electric potential which switches the MOS transistor MP 141 to the OFF state. In short, the sampling pulse signal SMP needs to fully swing within the range between the power supply electric potential and the GND potential. Because of so-called gate-feed-through phenomenon, such a transition in electric potential of the sampling pulse signal causes a variation in the electric potential of the output signal through the parasitic capacitance existing between the gate and the drain of the MOS transistor MP 141 and the MN 143. If the load capacitor C142 is reduced, the feed-through-caused variation in the output electric potential becomes large, and the retention of the signal becomes difficult. On this account, there is a limit to the reduction of the size of the load capacitor C142.
Further, in the second conventional example, the logic circuit which combines the data signal (input signal) with the controlling signal (sampling pulse signal) is realized by a circuit in which two MOS transistors (the MOS transistor MN 142 and the MN143) are cascade-connected with each other. For these MOS transistors, it is necessary to adopt transistors having a large element size so that these transistors are tolerable to a high operation voltage. Thus, in the second conventional example, a load capacitor for retaining signal needs to be acquired, and the number of the high-voltage resilient elements increases. For this reason, the planar dimension of the circuit inevitably increases. This is disadvantageous in that the chip size increases in a case of forming the circuit into an LSI.
For example, when either one of these level shifting circuit is adopted to a source driver circuit which serves as a liquid crystal driving circuit (i.e., one of display element driving circuit), the number of the level shifting circuits corresponding to the bit number of the display data are to be arranged for each output. This causes an increase in an planar dimension of an LSI chip.
In conclusion, either of the above described conventional level shifting circuits causes difficulties in reducing the scale of the entire circuit.